NBTI

Negative Bias Temperature Instability (NBTI) is a key reliability issue that is of immediate concern in p-channel MOS devices stressed with negative gate voltages. NBTI manifests as an increase in the threshold voltage and consequent decrease in drain current and transconductance. The degradation exhibits power law dependence with time.

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In the sub-micrometre devices nitrogen is incorporated into the gate oxide to address the issues like higher leakage current and boron penetration. However, incorporating nitrogen enhances NBTI. It seems possible that nitrogen-based gate stacks would be used even for the 65 nm node. This is because the development of High-K gate stacks, which are widely believed to be the eventual alternatives, is taking longer than expected.

It is widely believed that NBTI degradation is due to generation of interface traps, which are unsaturated silicon dangling bonds. One of the most successful models that has been able to explain NBTI phenomenon is the reaction diffusion model. This model proposes that the generation of interface traps is because of a hole induced electro-chemical reaction at the Si-SiO₂ interface. In the initial times the degradation is reaction rate controlled, however, with time the phenomenon becomes diffusion limited.

Recovery

Contribution from bulk traps

Bulk traps can also contribute to Vt degradation especially in the thick oxides. The relative contributions of interface and oxide traps on the Vt degradation is a matter of current research.

In the 2006 International Electron Devices Meeting, C. Shen and others presented a ground-breaking paper on ultra-fast NBTI measurements (100ns delay), which provided new reasons to believe that the Reaction-Diffusion model may not explain the NBTI mechanism correctly. Shen prefers the hole-trapping mechanism, whereby a hole gets trapped in a trap state, causing a shift in the threshold voltage.

References

• Dieter K. Schroder and Jeff A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing”, Journal of applied Physics, vol. 94, pp.1-18, July 2003.

• M. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation”, Microelectronics Reliability, vol. 45, no. 1, pp. 71-81, Jan. 2005.

• C. Shen et al., "Characterization and Physical Origin of Fast Vth Transient in NBTI of pMOSFETs with SiON Dielectric," IEDM Technical Digest, pp. 333-336, December 2006.

• D.K. Schroder, "Negative bias temperature instability: What do we understand?," Microelectronics Reliability, vol. 47, pp. 841-852, June 2007.