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32 nanometer

CMOS manufacturing
processes

10 µm
3 µm
1.5 µm
1 µm
800 nm (0.80 µm)
600 nm (0.60 µm)
350 nm (0.35 µm)
250 nm (0.25 µm)
180 nm (0.18 µm)
130 nm (0.13 µm)
90 nm
65 nm
45 nm
32 nm
22 nm
16 nm

The 32 nanometer (32 nm) process is the next step after the 45 nanometer process in CMOS manufacturing and fabrication. "32 nm" refers to the expected average half-pitch of a memory cell at this technology level. The two major chip rivals, Intel and AMD, are both working on a 32 nanometer process for logic, which uses significantly looser design rules. AMD has partnered with IBM on this process, as it did with the 45 nm process. The 32 nm process is due to arrive in the 2009-2010 timeframe.

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IMEC (Belgium) has recently demonstrated a 32 nm Flash patterning capability based on double patterning and immersion lithography. The introduction of double patterning may offset some of the cost advantages of moving from one node to the next, but may be unavoidable in order to reduce memory cell area.

TSMC similarly used double patterning combined with immersion lithography to produce a 32 nm node 0.183 square micrometer six-transistor SRAM cell in 2005.

IBM demonstrated a 0.143 square micrometer SRAM cell, produced using electron-beam lithography and optical lithography on the same layer. It was observed that the static noise margin (sensitivity to input voltage fluctuations) degraded significantly in going to such a small SRAM cell size. The poly gate pitch was 135 nm.

Intel showed the first 32nm test chips to the public on September 18, 2007 at the Intel Developer Forum. At the release, several technical details were disclosed. A second-generation high-k gate dielectric and metal gate were used. The cell size was 0.182 square micrometers and the chip contained almost 2 billion transistors. 193 nm immersion lithography was used for the critical layers, while 193 nm or 248 nm dry lithography was used on less critical layers.

Not to be outdone, in late October 2007, Samsung disclosed a 30 nm NAND Flash patterning process, using self-aligned double patterning. Starting from a 60 nm half-pitch pattern, new material was deposited and etched in between features to produce a 30 nm half-pitch pattern. Presumably, this can be repeated once more for 15 nm half-pitch.

The successors to 32 nm technology will be 22 nm, and then 16 nm technology per ITRS.