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16 nanometer

CMOS manufacturing
processes

10 µm
3 µm
1.5 µm
1 µm
800 nm (0.80 µm)
600 nm (0.60 µm)
350 nm (0.35 µm)
250 nm (0.25 µm)
180 nm (0.18 µm)
130 nm (0.13 µm)
90 nm
65 nm
45 nm
32 nm
22 nm
16 nm

The 16 nanometer (16 nm) node is the technology node following 22 nm node. The exact naming of these technology nodes comes from the International Technology Roadmap for Semiconductors (ITRS). By conservative estimates the 16 nm technology is expected to be reached by semiconductor companies in the 2018 timeframe.^[1] At that time, the typical half-pitch for a memory cell would be around 16 nm. However, in complying with its own "Architecture and Silicon Cadence Model",^[2] Intel will need to reach a new manufacturing process every two years. This would imply going to 16 nm as early as 2013.

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Assuming high-index immersion lithography is introduced for the 22 nm node by 2011, double patterning could be used to reach 16 nm. Multiple patterning can go even further, using any immersion lithography as a starting point.

Currently, very few 16 nm features are capable of being produced using reliable processes in mass quantity, with some notable attempts like carbon nanotubes. Even in these cases, the variation within any sample population is quite large and the compatibility of such exotic processes and materials with current mainstream ones present further issues.

Toshiba recently demonstrated 15 nm gate length and 10 nm fin width using a sidewall spacer process.^[3] In December 2007, Toshiba demonstrated a prototype memory unit which uses 15 nanometer thin lines ^[4] Fifteen nanometers is equivalent to 0.000015 millimeters

For comparison, the lattice constant, or distance between surface atoms, of unstrained silicon is 0.543 nm. Thus fewer than thirty atoms would form the insulating layer preventing leakage.

References

^ "Intel scientists find wall for Moore's Law", ZDNet, December 1, 2003.
^ Intel Architecture and Silicon Cadence – The Catalyst for Industry Innovation. Intel White Paper.
^ Kaneko, A; A Yagashita, K Yahashi, T Kubota, et al. (2005). "Sidewall transfer process and selective gate sidewall spacer formation technology for sub-15nm FinFET with elevated source/drain extension". IEEE International Electron Devices Meeting (IEDM 2005): 844-847. DOI:10.1109/IEDM.2005.1609488.
^ http://www.theinquirer.net/gb/inquirer/news/2007/12/13/nanometre-memory-tested